Advanced Electrically Erasable Programmable Read Only Memory (EEPROM) technology may be used to realize System-On-Chip (SOC) functionality. SOC technologies may require high performance, fast access, low voltage and low power operation EEPROMs, together with advanced CMOS processes. Often, a non-volatile memory may include flash memory for code storage and EEPROM memory for data storage. The EEPROM memory may require extremely high endurance (up to 1 million erase/program cycles) and byte-alterable functionality.
Traditionally, byte-alterable EEPROM memories have been based on a Floating-gate Tunnel Oxide (FLOTOX) cell and have been operated using Fowler-Nordheim (FN) tunneling both for write and erase operations. Each cell may include a tunneling area, a High Voltage (HV) select transistor, and a separate high-voltage (HV) select transistor at the drain side. Although FLOTOX memories may provide low power operation and may provide high endurance, FLOTOX memories may have a relatively large cell size.
Memory structures are discussed, for example, in the reference by Tao et al. entitled “Device Architecture And Reliability Aspects Of A Novel 1.22 μm2 EEPROM Cell In 0.18 μm Node For Embedded Applications” (Microelectronics Engineering, 72, 2004, pages 415-420), the disclosure of which is hereby incorporated herein in its entirety by reference. The EEPROM structure of the Tao publication may improve scalability while providing features such as byte-alterability, high endurance, and low power operation. More particularly, the EEPROM structure of the Tao publication may be based on a 2T-FN-NOR (2 transistor-FN-NOR) cell.
Further memory structures are discussed in U.S. Pat. No. 6,031,764 to Imamiya et al. entitled “Nonvolatile Semiconductor Memory Device,” the disclosure of which is hereby incorporated herein in its entirety by reference. As discussed in the Imamiya patent, a nonvolatile semiconductor device may include a memory cell array with, for example, NAND memory cells, a row decoder to select and drive word lines, and data sense amplifier/latch circuits to exchange data with the selected memory cells via bit lines. The memory cell array may be divided into blocks in a word line direction. The individual blocks are formed in wells formed separately in a semiconductor substrate. Each word line driven by the row decoder may be provided continuously by means of control transistors formed in the boundary areas between blocks. Turning off the control transistors may enable the data to be erased simultaneously block by block.
Notwithstanding the memory structures discussed above, there continues to exist a need in the art for improved memory structures and methods.